PNIASIC
HostProcessorInterface
Hardware Handshaking Line Descriptions
RESET
RESET is usually low. RESET must be toggled from low-high-low.
DRDY – Data Ready
DRDY is low after a RESET; after a command has been received and the data is ready, DRDY will be
high. It is recommended that the DRDY line always be used to ensure that the data is clocked out of the
PNI ASIC only when it is available. If it is determined that the DRDY line cannot be used due to lack of
I/O lines to the host processor, then the times listed in Cross Reference Colorable\ can be used to set open-
loop wait times. The values listed are the maximum delays from the end of the SCLK command until the
rise of the DRDY at each period select setting. The maximum delay occurs when the sensor being sampled
is in a zero field
Table 9: Maximum Delay for DRDY
Period Select Maximum Delay
SEN-S (3 VDC)
/32 500µS
/64 1.0 mS
/128 2.0 mS
/256 4.0 mS
/512 7.5 mS
/1024 15 mS
/2048 35.5 mS
/4096 60 mS
Operation
Basic operation will follow these steps. Refer to Figure 5 and Figure 6.
1. SSNOT is brought low.
2. Pulse RESET high (return to low state). You must RESET the PNI ASIC before every measurement.
3. Data is clocked in on the MOSI line. Once eight bits are read in, the PNI ASIC will execute the command.
4. The PNI ASIC will make the measurement. A measurement consists of forward biasing the sensor and
making a period count; then reverse biasing the sensor and counting again; and finally, taking the difference
between the two bias directions.
5. At the end of the measurement, the DRDY line is set to high indicating that the data is ready. In response to
the next 16 SCLK pulses, data is shifted out on the MISO line.
If you need to make another measurement, go to Step2. You can send another command after the reset. In this case,
keep SSNOT low. If you will not be using the PNI ASIC, set SSNOT to high to disable the SPI port.
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